A semiconductor test equipment for a large scale integrated circuit includes a large number of test pins as well as test functions. Each of the test functions for each test pin is calibrated prior to a test of a device under test in order to improve a measurement accuracy such as a propagation time. In general, this calibration is executed by transmitting a calibration data file to an appropriate circuit in the test equipment.
FIG. 2 shows an example of circuit structures for such a pre-test calibration in a conventional semiconductor test equipment. The semiconductor test equipment has a large number, for example 512 of drivers, exemplified by drivers 13, 23, and 33 for an IC (integrated circuit) device under test (hereinafter referred to as DUT) 1. The drivers 13, 23 . . . 33 are provided in the semiconductor test equipment to accommodate the maximum possible device pin numbers included in an IC device to be tested.
The driver 13 has a variable delay circuit 11 for a skew adjustment of clock timing in a test signal to be provided to a device pin P.sub.1. The value for the skew adjustment is transferred to a variable delay (VD) register 12. Similarly, for a device pin P.sub.2, a variable delay circuit 21 and a VD register 22 are provided, and for a device pin P.sub.n, a variable delay circuit 31 and a VD register 32 are respectively provided.
The calibration data such as the skew adjustment values for the device pins P.sub.1, P.sub.2 . . . P.sub.n are given to the VD registers 11, 21 . . . 31 from a calibration file "CAL FILE" memory 2. Thus, a skew of a test signal for each device pin is adjusted prior to the test of the DUT 1 so that, for example, the timings in the test signals for all the device pins coincide.
In general, a modern semiconductor test equipment has so called a pin multiple function to achieve a high-speed test signal generation and a complex driver waveform. Multiplex registers 27 . . . 37 shown in FIG. 2 are provided for channels corresponding to the even number of device pins to perform the pin multiple function. When a pin multiplex mode is set in the device pin P.sub.2, a gate 26 inhibits a P.sub.2 CLK signal, and as a result the output of driver 23 is inhibited. The P.sub.2 CLK signal passes through a gate 14 and is combined with a P.sub.1 CLK signal in an OR gate 15. Therefore, the P.sub.1 CLK and P.sub.2 CLK signals are output through the driver 13 to be supplied to the device pin P.sub.1 of the DUT 1.
That is, by the operation of the OR gate 15, a clock signal of an even number pin and a clock signal of an odd number pin are multiplexed to form a combined signal which is output to the odd number pin. This produces a test signal which is two times faster than a clock signal in each channel of circuit corresponding to one device pin. In the example of FIG. 2, the only circuit channels corresponding to the even number device pins have multiplex registers 27 and 37 for the pin multiplex mode.
As noted above, the calibration data in the CAL FILE memory 2 is transmitted to the VD register 12, 22, and 32. The calibration data for the skew adjustment in the normal mode would be different from that of the pin multiplex mode, even for the same device pin, because of differences in signal propagation times since signal transmission paths are different between the two modes. Therefore, the CAL FILE memory 2 stores different calibration data, normal mode data (NV) and pin multiplex mode data (PV) for each device pin as shown in FIG. 2. Since the number of device pins is large, 512 for example, and the different calibration data are required for the normal mode and the multiplex mode, the capacity of the calibration file memory 2 to store the calibration data for all of the device pins becomes very large.
In addition, since many combinations between the device pins are required, the CAL FILE memory 2 needs a large number of data files F1, F2 . . . Fm. Therefore, the CAL FILE memory 2 needs the memory capacity of n.times.m.times.x (bits) where a word length of the calibration data is x bits, a total number of device pins is n and the number of possible combination of device pins is m.
The calibration data for the CAL FILE memory 2 is created as explained in FIG. 5 which shows an example of user programming in the conventional semiconductor test equipment of FIG. 2.
In the user program of FIG. 2, first, all the device pins P.sub.1 -P.sub.n for a first test "TEST 1" are set to the normal mode. A calibration data file "file 1" is created under this condition for all the device pins P.sub.1 -P.sub.n. That is, a calibration operation for each device pin is executed in this step for forming the calibration data file. When the calibration operation is completed, the data file for all the pin data is created.
Next, in a second test "TEST 2", the device pin P.sub.2 is set in the multiple pin mode and other device pins are set in the normal mode. In this situation, because the conditions of signal propagation routes to the corresponding device pins are different from that in the TEST 1, a separate calibration data file is needed. Therefore, a calibration data file "file 2" is created in this step.
Next, the device pin P.sub.2 and the device pin P.sub.n in the "TEST m" are set in the multiple pin mode, and other device pins are set in the normal mode. In this situation, the condition of the signal propagation paths are different from that in the TEST 1 and TEST 2. Therefore, another calibration data file "file m" is created in this step. In the conventional semiconductor test equipment, the number m of files in the calibration file memory 2 will increase with the increase in the number of tests.
Next, for a test "TEST (m+1)", all of the device pins P.sub.1 -P.sub.n are set in the normal mode. The condition of the signal propagation for this setting is the same as in the TEST 1. Therefore, the calibration will not be executed in this step and the content of the "file 1" is transmitted to each of the VD registers 12, 22 . . . 32. That is, only a transmission of the calibration data is executed here.
Next, for a test "TEST (m+2)", all of the device pins P.sub.1 -P.sub.n are once again set in the normal mode. In this situation, the conditions of signal propagation paths to the corresponding device pins are the same as that in the "TEST 1" or the "TEST (m+1)", the calibration data of which are already transmitted to the VD registers 12, 22 . . . 32. Thus, theoretically, in this step, it is not necessary to newly create a description of calibration instruction by the user program. However, since the user program is provided in this manner, the file transmitting operation is unconditionally executed, which lowers a test throughput. This is a result caused by opening a CALL CAL (call calibration) sentence to the user.
FIG. 6 shows an algorithm of a conventional CALL CAL sentence. At a step S11, it is determined whether there exists a CAL FILE of the same name. If the same CAL FILE (calibration file) exists, the algorithm moves to a step S14 wherein the calibration file data is transmitted to the VD registers.
If the CAL FILE of the same name does not exist, a CAL operation is executed in a step S12 so that a CAL FILE is created in a step S13. In general, the execution time of the CAL operation requires a significant length of time compared with the transmission time of the CAL FILE.
After transmitting the CALFILE value created like this manner, the operation based on TEST sentences is proceeded. Thus, in the conventional test equipment described above, there is a problem in that the data file memory for the calibration data requires a large capacity. Another problem in the conventional test equipment is that a significantly long time is required to create the calibration data and to transmit such data.